1. Field of the Invention
The present invention relates to exposure data preparing apparatuses, exposure data preparing methods and charged particle beam exposure apparatuses, and more particularly to an apparatus and a method for preparing exposure data that is used in exposing a pattern on a semiconductor wafer, and an exposure apparatus in which the method is applied.
2. Description of the Prior Art
Generally, an electron beam exposure apparatus is used to produce a mask for a semiconductor integrated circuit (LSI). The electron beam exposure apparatus exposes a predetermined pattern on an exposed area on a semiconductor wafer. The exposed area on the wafer is divided into areas, each area called a field and having a predetermined size. The field is further divided into smaller areas called sub-fields, each sub-field having a predetermined size.
LSI design data is provided for each sub-field. Singular placement pattern data places an exposure pattern on a sub-field by itself. Matrix placement pattern data places a plurality of exposure patterns on associated sub-fields using the same data. Each set of data contains information relating to placement of an exposure pattern, the number of patterns placed, the identification number for placement, and a range of placement. There are four types of pattern data: singular placement pattern data; singular block exposure pattern data capable of exposing a plurality of patterns with one beam shot; matrix placement block exposure pattern data including information relating to position of placement; and matrix placement pattern including information relating to position of placement.
A description will now be given of how exposure data is prepared according to the prior art. Data preparation method according to Japanese Laid-Open Patent Application No. 5-74691 that the applicant has filed will be discussed. As shown in FIG. 1A, a field which is to be exposed is divided into a total of 49 (7.times.7) sub-fields. A matrix placement pattern 1 that derives from LSI design data is placed on the sub-fields. According to this placement, the matrix placement pattern data is registered in each of the 49 sub-fields.
The matrix placement pattern 1 comprises a matrix placement pattern A for 9 (3.times.3) sub-fields for a memory pattern or the like; four matrix placement sub-patterns B through E surrounding the matrix placement sub-pattern A; and singular placement sub-fields 2 disposed at the periphery of the matrix and surrounding the matrix placement sub-patterns B through E. The matrix placement pattern 1 is surrounded by 24 singular placement sub-fields.
A dosage of beam applied (beam dosage) is determined for each pattern and for each sub-field. For correction of a beam dosage, matrix identification process of the placement pattern 1 is conducted. In this identification process, the placement pattern 1 is segmented into the singular placement sub-fields disposed at the periphery of the matrix, and the sub-fields (the matrix placement sub-patterns B through E) inside the matrix. The sub-fields at the periphery of the matrix are expanded.
As a result of this expansion, the density of the exposure pattern occupying a given sub-field is determined so that a proximity effect is corrected. The proximity effect occurs between a boundary of the exposure pattern to be corrected and an adjacent exposure pattern. The proximity effect is denoted as .epsilon. .mu.m!. In the conventional technology, correction of the proximity effect is conducted for each sub-field such that a beam projection dosage and a dimension of area to which the beam is projected are corrected. Thereafter, the corrected pattern data is converted into a format compatible with exposure data for an electron beam exposure apparatus. Thus, exposure data based on design data is prepared.
However, the conventional method of preparing exposure data has the following problem.
(1) In the matrix identification carried out in order to correct a beam dosage for each pattern, the matrix placement pattern 1 is segmented into the singular placement sub-fields at the periphery of the matrix, and the sub-fields inside the matrix, as shown in FIG. 1A. Further, the sub-fields at the periphery of the matrix are expanded. According to this approach, matrix placement patterns 2 and 3 as shown in FIGS. 1B and 1C, respectively, are recognized as individual singular placement sub-fields. In the matrix placement pattern 2, five rows of five aligned sub-fields are arranged, the two adjacent rows being spaced apart by one row. In the matrix placement pattern 3, five rows of five aligned sub-fields are arranged, the two adjacent rows being horizontally displaced from each other by one sub-field.
When sub-fields are processed as singular placement sub-fields, it is necessary to determine the pattern density for correction of the proximity effect that occurs in relationship to the surrounding sub-fields. If a large number of sub-fields are to be processed, a large volume of data is to be processed accordingly. Thus, a high-speed correction of pattern data is prevented.
(2) Memory devices that are currently produced require LSI design data that contains a large volume of matrix placement pattern data. Further, placement of exposure patterns has become increasingly complex. Therefore, a long time is required in order to recognize a matrix.
(3) According to the conventional technology, a beam dosage is determined for individual sub-fields. It is necessary to obtain a beam dosage for the exposure patterns applied to the entirety of a chip if the design data contains matrix placement pattern data or block exposure pattern data so that it is necessary to determine whether or not to prepare a supplementary exposure pattern for correction of proximity effect. The determination as to whether or not a supplementary exposure pattern is to be prepared requires a long time according to the conventional technology.
As the capacity of an LSI increases and its function is enhanced, the time required to process data by a computer increases greatly, thereby making it difficult to carry out correction of pattern data for a large-scale memory or logic device.